URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] [xilinx_dcm.v] - Rev 173

Rev	Log message	Author	Age	Path
173	Jay Aurabind's contribution of a port to the Nexys 3 board from Digilent. Thanks!!	rfajardo	4249d 09h	/minsoc/trunk/rtl/verilog/xilinx_dcm.v
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4828d 06h	/minsoc/trunk/rtl/verilog/xilinx_dcm.v
62	Wrapping different family modules of same manufacturer in a single module. minsoc_clock_manager.v: uses fpga manufacturer wrappers xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module altera_pll.v: selects between different Altera FPGA families and implements the module	rfajardo	4958d 13h	/minsoc/trunk/rtl/verilog/xilinx_dcm.v