URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [xilinx_dcm.v] - Rev 88

Rev	Log message	Author	Age	Path
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4864d 15h	/minsoc/trunk/rtl/verilog/xilinx_dcm.v
62	Wrapping different family modules of same manufacturer in a single module. minsoc_clock_manager.v: uses fpga manufacturer wrappers xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module altera_pll.v: selects between different Altera FPGA families and implements the module	rfajardo	4994d 22h	/minsoc/trunk/rtl/verilog/xilinx_dcm.v