URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [sim/] [run/] [generate_bench] - Rev 56

Rev	Log message	Author	Age	Path
30	minsoc SoC documentation had 2 small typo corrections. Performance penalty due to addition of register addresses was a wrong assumption. On project description "is composed by" -> "consists of". Thanks to Wojciech A. Koszek. howto, at some places the howto did not tell the path from the files being talked about. I tried to always specify the path for every commented file. Scripts for running the simulation called bash instead of sh. For compatibility reasons sh is now used, this should affect noone. Scripts do not use bash specific commands and generally every UNIX like computer has sh. Thanks again to Wojciech A. Koszek, who adapted that to port it to FreeBSD.	rfajardo	5302d 19h	/minsoc/trunk/sim/run/generate_bench
17	Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v. send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart) If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.	rfajardo	5514d 14h	/minsoc/trunk/sim/run/generate_bench
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5574d 17h	/minsoc/trunk/sim/run/generate_bench