OpenCores

URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [sw/] [support/] [except.S] - Rev 83

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
74	or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined macro) to find out if we need the underscore as prefix to reference C functions (its assembly labels) or not. except.S and reset.S use CLABLE to call externally defined C functions. This should avoid problems compiling firmware with old or new toolchain. support/common.mk updated, reset-nocache.o and reset-icdc.o are dependent on or1200.h	rfajardo	4974d 10h	/minsoc/trunk/sw/support/except.S
53	Indentation, deleting redundant files and adding externals	ConX.	4994d 18h	/minsoc/trunk/sw/support/except.S
50	Removing unused firmware files, respective to or1ksim actually. Removing the inclusion of the removed file mc.h in reset.S, probably required by or1ksim at some point. Reworked except.S to use a macro instead of repeating the same procedure 16 times or so. Explanation added to the macro as a leading comment.	rfajardo	5021d 17h	/minsoc/trunk/sw/support/except.S
47	Firmware updated to work with gcc-4.5. It is actually working just fine and gcc-4.5 assembly code seems a lot cleaner. I noticed that by increasing the free stack space for the interrupt handler by 130 made the resulting firmware not work. I assume it is because 130 is not aligned 130%4 = 2 and the stack simply does not work then. Instead I'm freeing the previous 116 plus 128 (for 32 registers as mentioned by Jeremy) and it works.	rfajardo	5024d 14h	/minsoc/trunk/sw/support/except.S
36	utils: -adding a 32 to 8 bit Wishbone bridge to connect 8 bit modules to the MinSoC interconnect. -adding a Linux driver for parallel cables for the adv_jtag_bridge. It circumvents the necessity of privilege to run adv_jtag_bridge with cables xpc3 and xess. sw/support: support library has been made completely standalone. That means, it is now independent from uClib and/or newlib. Thanks to Wojciech A. Koszek for his contribution on this. sw/drivers: a driver library has been included, which supply drivers for the OpenRISC timer; and for UART, Ethernet, I2C, and CAN modules from OpenCores. sw/uart and sw/eth: they don't provide code to control the UART and Ethernet controllers anymore. They use the drivers library instead. Documentation: -FAQ extended: -table of contents -explanation of how to use the 32 to 8 bit Wishbone bridge -how to make adv_jtag_bridge work without privilege requirement for xess or xpc3 -explanation of locking problem of xpc_usb cable -explanation of what to do if the cable is built on-board -INSTALL: -patching of gdb only required if version is 6.8, explanation on FAQ now. -HOWTO: -instruct to compile drivers library -remove line numbers information on what to edit, better leave it to be found only by the informed context. -adv_jtag_bridge execution now without 'sudo'. Note included that 'sudo' is required for Linux and xess or xpc3. Reference to FAQ to avoid this requirement.	rfajardo	5167d 12h	/minsoc/trunk/sw/support/except.S
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5573d 17h	/minsoc/trunk/sw/support/except.S

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.