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[/] [mkjpeg/] [branches/] [16rgb/] [trunk/] [tb/] [COMPILE.do] - Rev 48

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48 mikel262 5526d 20h /mkjpeg/branches/16rgb/trunk/tb/COMPILE.do
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5751d 14h /mkjpeg/branches/16rgb/trunk/tb/COMPILE.do
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5753d 10h /mkjpeg/branches/16rgb/trunk/tb/COMPILE.do
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5754d 07h /mkjpeg/branches/16rgb/trunk/tb/COMPILE.do
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5759d 08h /mkjpeg/branches/16rgb/trunk/tb/COMPILE.do
25 moved from branch to trunk mikel262 5761d 21h /mkjpeg/branches/16rgb/trunk/tb/COMPILE.do

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