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[/] [mlite/] [tags/] [V3_0/] [vhdl/] [mem_ctrl.vhd] - Rev 350

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350 root 5620d 23h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
140 This commit was manufactured by cvs2svn to create tag 'V3_0'. 6721d 12h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6721d 12h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
129 Added reset_in to sensitivity list rhoads 7220d 10h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
128 Reset all registers, constants now upper case. rhoads 7338d 22h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7538d 12h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
95 register mem_write and mem_byte_sel for speed calculations rhoads 8061d 15h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
89 Use address_reg instead of address_data to break timing slow down rhoads 8063d 09h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
72 accurate_timing, cleanup, pipeline rhoads 8071d 10h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
56 Altera, added byte_sel_reg for tigher timing and avoid possible glitches rhoads 8079d 15h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
49 Fix pause while writting rhoads 8090d 11h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
47 Altera rhoads 8097d 11h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
43 Renamed M-lite to Plasma rhoads 8177d 11h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8209d 17h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
8 Preparing to use dual-port memory for registers. rhoads 8246d 11h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
7 Made writes 4 cycles, improved mem_ctrl.vhd rhoads 8251d 18h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
6 JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts. rhoads 8255d 16h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd
2 MIPS-lite CPU core rhoads 8474d 16h /mlite/tags/V3_0/vhdl/mem_ctrl.vhd

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