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[/] [mlite/] [tags/] [V3_0/] [vhdl/] [mlite_pack.vhd] - Rev 350

Rev	Log message	Author	Age	Path
350		root	5620d 23h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
140	This commit was manufactured by cvs2svn to create tag 'V3_0'.		6721d 12h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
139	Major changes -- updated to Plasma Version 3	rhoads	6721d 12h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7201d 10h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
128	Reset all registers, constants now upper case.	rhoads	7338d 22h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
125	Fixed pc_source_type comment.	rhoads	7357d 11h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
116	Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7538d 12h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
96	Simplify take_branch	rhoads	8061d 15h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
91	Removed unused alu_function_type entries	rhoads	8063d 09h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
70	pipeline	rhoads	8071d 10h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
62	updated LPM functions; mem_none->mem_fetch	rhoads	8079d 15h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
50	Update prototypes	rhoads	8090d 11h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
47	Altera	rhoads	8097d 12h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
44	Fixed signed 64-bit multiply	rhoads	8175d 01h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
43	Renamed M-lite to Plasma	rhoads	8177d 12h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8209d 17h	/mlite/tags/V3_0/vhdl/mlite_pack.vhd