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[/] [mlite/] [tags/] [V3_0/] [vhdl/] [mult.vhd] - Rev 350

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350 root 5620d 23h /mlite/tags/V3_0/vhdl/mult.vhd
140 This commit was manufactured by cvs2svn to create tag 'V3_0'. 6721d 12h /mlite/tags/V3_0/vhdl/mult.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6721d 12h /mlite/tags/V3_0/vhdl/mult.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7201d 10h /mlite/tags/V3_0/vhdl/mult.vhd
128 Reset all registers, constants now upper case. rhoads 7338d 22h /mlite/tags/V3_0/vhdl/mult.vhd
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7500d 00h /mlite/tags/V3_0/vhdl/mult.vhd
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7538d 11h /mlite/tags/V3_0/vhdl/mult.vhd
99 correct upper 32-bits for mult(-1,-1) rhoads 7958d 09h /mlite/tags/V3_0/vhdl/mult.vhd
97 added documentation rhoads 8027d 13h /mlite/tags/V3_0/vhdl/mult.vhd
90 Now multiplies two bits at a time rhoads 8063d 09h /mlite/tags/V3_0/vhdl/mult.vhd
47 Altera rhoads 8097d 11h /mlite/tags/V3_0/vhdl/mult.vhd
45 Fixed signed 64-bit multiply rhoads 8175d 00h /mlite/tags/V3_0/vhdl/mult.vhd
43 Renamed M-lite to Plasma rhoads 8177d 11h /mlite/tags/V3_0/vhdl/mult.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8209d 17h /mlite/tags/V3_0/vhdl/mult.vhd
23 Fixed div -x/y. rhoads 8234d 10h /mlite/tags/V3_0/vhdl/mult.vhd
18 Fixed "divu $3,$4". "Div $3,$4" still has bug if $3*$4<0. rhoads 8236d 10h /mlite/tags/V3_0/vhdl/mult.vhd
7 Made writes 4 cycles, improved mem_ctrl.vhd rhoads 8251d 18h /mlite/tags/V3_0/vhdl/mult.vhd
2 MIPS-lite CPU core rhoads 8474d 16h /mlite/tags/V3_0/vhdl/mult.vhd

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