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[/] [mlite/] [tags/] [V3_0/] [vhdl/] [reg_bank.vhd] - Rev 350

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350 root 5620d 23h /mlite/tags/V3_0/vhdl/reg_bank.vhd
140 This commit was manufactured by cvs2svn to create tag 'V3_0'. 6721d 12h /mlite/tags/V3_0/vhdl/reg_bank.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6721d 12h /mlite/tags/V3_0/vhdl/reg_bank.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7201d 10h /mlite/tags/V3_0/vhdl/reg_bank.vhd
128 Reset all registers, constants now upper case. rhoads 7338d 22h /mlite/tags/V3_0/vhdl/reg_bank.vhd
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7424d 12h /mlite/tags/V3_0/vhdl/reg_bank.vhd
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7538d 12h /mlite/tags/V3_0/vhdl/reg_bank.vhd
108 changed interrupt vector from 0x30 to 0x3c rhoads 7812d 08h /mlite/tags/V3_0/vhdl/reg_bank.vhd
88 Cleanup spaces rhoads 8063d 09h /mlite/tags/V3_0/vhdl/reg_bank.vhd
74 pause in rhoads 8071d 10h /mlite/tags/V3_0/vhdl/reg_bank.vhd
55 Altera rhoads 8079d 15h /mlite/tags/V3_0/vhdl/reg_bank.vhd
48 Altera rhoads 8090d 11h /mlite/tags/V3_0/vhdl/reg_bank.vhd
47 Altera rhoads 8097d 11h /mlite/tags/V3_0/vhdl/reg_bank.vhd
43 Renamed M-lite to Plasma rhoads 8177d 12h /mlite/tags/V3_0/vhdl/reg_bank.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8209d 17h /mlite/tags/V3_0/vhdl/reg_bank.vhd
24 Disable interrupts upon reset. rhoads 8234d 10h /mlite/tags/V3_0/vhdl/reg_bank.vhd
12 Better support for dual-port memories, removed old method rhoads 8240d 10h /mlite/tags/V3_0/vhdl/reg_bank.vhd
9 Support for generic_tpram dual-port RAM rhoads 8245d 14h /mlite/tags/V3_0/vhdl/reg_bank.vhd
8 Preparing to use dual-port memory for registers. rhoads 8246d 11h /mlite/tags/V3_0/vhdl/reg_bank.vhd
6 JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts. rhoads 8255d 16h /mlite/tags/V3_0/vhdl/reg_bank.vhd

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