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[/] [mlite/] [tags/] [V3_0/] [vhdl/] [tbench.vhd] - Rev 350

Rev	Log message	Author	Age	Path
350		root	5620d 23h	/mlite/tags/V3_0/vhdl/tbench.vhd
140	This commit was manufactured by cvs2svn to create tag 'V3_0'.		6721d 12h	/mlite/tags/V3_0/vhdl/tbench.vhd
139	Major changes -- updated to Plasma Version 3	rhoads	6721d 12h	/mlite/tags/V3_0/vhdl/tbench.vhd
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7201d 10h	/mlite/tags/V3_0/vhdl/tbench.vhd
128	Reset all registers, constants now upper case.	rhoads	7338d 22h	/mlite/tags/V3_0/vhdl/tbench.vhd
106	better test mem_pause	rhoads	7815d 10h	/mlite/tags/V3_0/vhdl/tbench.vhd
102	permit testing mem_pause	rhoads	7816d 10h	/mlite/tags/V3_0/vhdl/tbench.vhd
55	Altera	rhoads	8079d 15h	/mlite/tags/V3_0/vhdl/tbench.vhd
51	GENERIC	rhoads	8090d 11h	/mlite/tags/V3_0/vhdl/tbench.vhd
48	Altera	rhoads	8090d 11h	/mlite/tags/V3_0/vhdl/tbench.vhd
47	Altera	rhoads	8097d 11h	/mlite/tags/V3_0/vhdl/tbench.vhd
43	Renamed M-lite to Plasma	rhoads	8177d 12h	/mlite/tags/V3_0/vhdl/tbench.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8209d 17h	/mlite/tags/V3_0/vhdl/tbench.vhd
8	Preparing to use dual-port memory for registers.	rhoads	8246d 11h	/mlite/tags/V3_0/vhdl/tbench.vhd
7	Made writes 4 cycles, improved mem_ctrl.vhd	rhoads	8251d 18h	/mlite/tags/V3_0/vhdl/tbench.vhd
6	JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts.	rhoads	8255d 16h	/mlite/tags/V3_0/vhdl/tbench.vhd
2	MIPS-lite CPU core	rhoads	8474d 17h	/mlite/tags/V3_0/vhdl/tbench.vhd