OpenCores

URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] [mlite_cpu.vhd] - Rev 350

Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
350		root	5828d 06h	/mlite/trunk/vhdl/mlite_cpu.vhd
280	Fix comment	rhoads	6252d 18h	/mlite/trunk/vhdl/mlite_cpu.vhd
264	Latch address and byte_we in mem_ctrl.vhd	rhoads	6279d 04h	/mlite/trunk/vhdl/mlite_cpu.vhd
203	Fixed stages comment	rhoads	6518d 05h	/mlite/trunk/vhdl/mlite_cpu.vhd
202	Defined outputing PC as stage #0	rhoads	6518d 05h	/mlite/trunk/vhdl/mlite_cpu.vhd
194	Implemented BREAK and SYSCALL opcodes	rhoads	6583d 01h	/mlite/trunk/vhdl/mlite_cpu.vhd
139	Major changes -- updated to Plasma Version 3	rhoads	6928d 18h	/mlite/trunk/vhdl/mlite_cpu.vhd
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7408d 17h	/mlite/trunk/vhdl/mlite_cpu.vhd
128	Reset all registers, constants now upper case.	rhoads	7546d 04h	/mlite/trunk/vhdl/mlite_cpu.vhd
124	Holger Lohn's fix for interrupts when 3-state pipeline enabled.	rhoads	7564d 17h	/mlite/trunk/vhdl/mlite_cpu.vhd
120	Make generics "GENERIC"	rhoads	7707d 07h	/mlite/trunk/vhdl/mlite_cpu.vhd
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7745d 18h	/mlite/trunk/vhdl/mlite_cpu.vhd
96	Simplify take_branch	rhoads	8268d 21h	/mlite/trunk/vhdl/mlite_cpu.vhd
83	Updated comments, accurate_timing on by default	rhoads	8270d 15h	/mlite/trunk/vhdl/mlite_cpu.vhd
73	pipeline, better reset	rhoads	8278d 17h	/mlite/trunk/vhdl/mlite_cpu.vhd
60	reset control	rhoads	8286d 22h	/mlite/trunk/vhdl/mlite_cpu.vhd
47	Altera	rhoads	8304d 18h	/mlite/trunk/vhdl/mlite_cpu.vhd
43	Renamed M-lite to Plasma	rhoads	8384d 18h	/mlite/trunk/vhdl/mlite_cpu.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8416d 23h	/mlite/trunk/vhdl/mlite_cpu.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.