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[/] [mlite/] [trunk/] [vhdl/] [mlite_cpu.vhd] - Rev 350

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Rev	Log message	Author	Age	Path
350		root	5576d 21h	/mlite/trunk/vhdl/mlite_cpu.vhd
280	Fix comment	rhoads	6001d 09h	/mlite/trunk/vhdl/mlite_cpu.vhd
264	Latch address and byte_we in mem_ctrl.vhd	rhoads	6027d 19h	/mlite/trunk/vhdl/mlite_cpu.vhd
203	Fixed stages comment	rhoads	6266d 20h	/mlite/trunk/vhdl/mlite_cpu.vhd
202	Defined outputing PC as stage #0	rhoads	6266d 20h	/mlite/trunk/vhdl/mlite_cpu.vhd
194	Implemented BREAK and SYSCALL opcodes	rhoads	6331d 16h	/mlite/trunk/vhdl/mlite_cpu.vhd
139	Major changes -- updated to Plasma Version 3	rhoads	6677d 09h	/mlite/trunk/vhdl/mlite_cpu.vhd
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7157d 08h	/mlite/trunk/vhdl/mlite_cpu.vhd
128	Reset all registers, constants now upper case.	rhoads	7294d 19h	/mlite/trunk/vhdl/mlite_cpu.vhd
124	Holger Lohn's fix for interrupts when 3-state pipeline enabled.	rhoads	7313d 08h	/mlite/trunk/vhdl/mlite_cpu.vhd
120	Make generics "GENERIC"	rhoads	7455d 22h	/mlite/trunk/vhdl/mlite_cpu.vhd
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7494d 09h	/mlite/trunk/vhdl/mlite_cpu.vhd
96	Simplify take_branch	rhoads	8017d 12h	/mlite/trunk/vhdl/mlite_cpu.vhd
83	Updated comments, accurate_timing on by default	rhoads	8019d 06h	/mlite/trunk/vhdl/mlite_cpu.vhd
73	pipeline, better reset	rhoads	8027d 08h	/mlite/trunk/vhdl/mlite_cpu.vhd
60	reset control	rhoads	8035d 13h	/mlite/trunk/vhdl/mlite_cpu.vhd
47	Altera	rhoads	8053d 09h	/mlite/trunk/vhdl/mlite_cpu.vhd
43	Renamed M-lite to Plasma	rhoads	8133d 09h	/mlite/trunk/vhdl/mlite_cpu.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8165d 14h	/mlite/trunk/vhdl/mlite_cpu.vhd

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