OpenCores
URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] [mult.vhd] - Rev 350

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
350 root 5828d 05h /mlite/trunk/vhdl/mult.vhd
345 Commented out optional mult speedup rhoads 5899d 21h /mlite/trunk/vhdl/mult.vhd
196 Explained how to remove mult.vhd and use SW multiplication and division. rhoads 6565d 21h /mlite/trunk/vhdl/mult.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6928d 18h /mlite/trunk/vhdl/mult.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7408d 16h /mlite/trunk/vhdl/mult.vhd
128 Reset all registers, constants now upper case. rhoads 7546d 04h /mlite/trunk/vhdl/mult.vhd
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7707d 06h /mlite/trunk/vhdl/mult.vhd
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7745d 18h /mlite/trunk/vhdl/mult.vhd
99 correct upper 32-bits for mult(-1,-1) rhoads 8165d 15h /mlite/trunk/vhdl/mult.vhd
97 added documentation rhoads 8234d 19h /mlite/trunk/vhdl/mult.vhd
90 Now multiplies two bits at a time rhoads 8270d 15h /mlite/trunk/vhdl/mult.vhd
47 Altera rhoads 8304d 17h /mlite/trunk/vhdl/mult.vhd
45 Fixed signed 64-bit multiply rhoads 8382d 06h /mlite/trunk/vhdl/mult.vhd
43 Renamed M-lite to Plasma rhoads 8384d 18h /mlite/trunk/vhdl/mult.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8416d 23h /mlite/trunk/vhdl/mult.vhd
23 Fixed div -x/y. rhoads 8441d 16h /mlite/trunk/vhdl/mult.vhd
18 Fixed "divu $3,$4". "Div $3,$4" still has bug if $3*$4<0. rhoads 8443d 17h /mlite/trunk/vhdl/mult.vhd
7 Made writes 4 cycles, improved mem_ctrl.vhd rhoads 8459d 00h /mlite/trunk/vhdl/mult.vhd
2 MIPS-lite CPU core rhoads 8681d 22h /mlite/trunk/vhdl/mult.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.