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[/] [mlite/] [trunk/] [vhdl/] [reg_bank.vhd] - Rev 350

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Rev Log message Author Age Path
350 root 5576d 22h /mlite/trunk/vhdl/reg_bank.vhd
344 Fixed compiler warning rhoads 5648d 14h /mlite/trunk/vhdl/reg_bank.vhd
333 Updated Altera lpm_ram_dp usage for Cyclone FPGAs rhoads 5705d 12h /mlite/trunk/vhdl/reg_bank.vhd
261 Removed commented out lines rhoads 6027d 21h /mlite/trunk/vhdl/reg_bank.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6677d 11h /mlite/trunk/vhdl/reg_bank.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7157d 09h /mlite/trunk/vhdl/reg_bank.vhd
128 Reset all registers, constants now upper case. rhoads 7294d 21h /mlite/trunk/vhdl/reg_bank.vhd
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7380d 11h /mlite/trunk/vhdl/reg_bank.vhd
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7494d 11h /mlite/trunk/vhdl/reg_bank.vhd
108 changed interrupt vector from 0x30 to 0x3c rhoads 7768d 07h /mlite/trunk/vhdl/reg_bank.vhd
88 Cleanup spaces rhoads 8019d 08h /mlite/trunk/vhdl/reg_bank.vhd
74 pause in rhoads 8027d 09h /mlite/trunk/vhdl/reg_bank.vhd
55 Altera rhoads 8035d 14h /mlite/trunk/vhdl/reg_bank.vhd
48 Altera rhoads 8046d 10h /mlite/trunk/vhdl/reg_bank.vhd
47 Altera rhoads 8053d 10h /mlite/trunk/vhdl/reg_bank.vhd
43 Renamed M-lite to Plasma rhoads 8133d 11h /mlite/trunk/vhdl/reg_bank.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8165d 16h /mlite/trunk/vhdl/reg_bank.vhd
24 Disable interrupts upon reset. rhoads 8190d 09h /mlite/trunk/vhdl/reg_bank.vhd
12 Better support for dual-port memories, removed old method rhoads 8196d 09h /mlite/trunk/vhdl/reg_bank.vhd
9 Support for generic_tpram dual-port RAM rhoads 8201d 13h /mlite/trunk/vhdl/reg_bank.vhd

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