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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Rev 84

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Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4106d 17h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4146d 17h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4214d 22h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
43	made the core parameters generics	JonasDC	4218d 16h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4237d 17h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4243d 01h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4254d 17h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4258d 23h	/mod_sim_exp/tags/Release_1.1/bench/vhdl/mod_sim_exp_core_tb.vhd

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