URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] [core/] [cell_1b_mux.vhd] - Rev 80

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4132d 05h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/cell_1b_mux.vhd
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4172d 05h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/cell_1b_mux.vhd
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4279d 10h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/cell_1b_mux.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4280d 05h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/cell_1b_mux.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4284d 11h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/cell_1b_mux.vhd