URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] [core/] [operand_mem.vhd] - Rev 96

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4183d 20h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/operand_mem.vhd
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4223d 20h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/operand_mem.vhd
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4310d 18h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/operand_mem.vhd
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4315d 20h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/operand_mem.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4331d 20h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/operand_mem.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4336d 02h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/operand_mem.vhd