URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] [core/] [sys_first_cell_logic.vhd] - Rev 80

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4159d 12h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/sys_first_cell_logic.vhd
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4199d 13h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/sys_first_cell_logic.vhd
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4291d 22h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/sys_first_cell_logic.vhd