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[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] [core/] [sys_pipeline.vhd] - Rev 96

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80 renamed to version 1.1 to follow the versioning system JonasDC 4148d 03h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/sys_pipeline.vhd
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.		 JonasDC 4188d 03h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/sys_pipeline.vhd
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4279d 03h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/sys_pipeline.vhd
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4280d 00h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/sys_pipeline.vhd
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4280d 07h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/sys_pipeline.vhd
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4280d 12h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/sys_pipeline.vhd
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4280d 13h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/sys_pipeline.vhd
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4281d 02h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/sys_pipeline.vhd

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