URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] [interface/] [plb/] [mod_sim_exp_IPcore.vhd] - Rev 80

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4168d 03h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4208d 04h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4280d 02h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd