URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 80

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4168d 04h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/user_logic.vhd
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4208d 04h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/user_logic.vhd
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4276d 09h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/user_logic.vhd
43	made the core parameters generics	JonasDC	4280d 03h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/user_logic.vhd
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4286d 10h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/user_logic.vhd
40	adjusted core instantiation to new core module name	JonasDC	4294d 15h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/user_logic.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4320d 10h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/user_logic.vhd