URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] [core/] [fifo_generic.vhd] - Rev 93

Rev	Log message	Author	Age	Path
79	Tag for version 1.3 (with new ram style	JonasDC	4148d 00h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/fifo_generic.vhd
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4161d 04h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/fifo_generic.vhd
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4171d 22h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/fifo_generic.vhd
55	updated resource usage in comments	JonasDC	4175d 22h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/fifo_generic.vhd
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4175d 22h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/fifo_generic.vhd