URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] [core/] [modulus_ram_gen.vhd] - Rev 94

Rev	Log message	Author	Age	Path
79	Tag for version 1.3 (with new ram style	JonasDC	4183d 20h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/modulus_ram_gen.vhd
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4205d 00h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/modulus_ram_gen.vhd