URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] [core/] [operand_mem.vhd] - Rev 93

Rev	Log message	Author	Age	Path
79	Tag for version 1.3 (with new ram style	JonasDC	4148d 01h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/operand_mem.vhd
75	made rw_address a vector of a fixed width	JonasDC	4156d 09h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/operand_mem.vhd
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4161d 05h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/operand_mem.vhd
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4169d 05h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/core/operand_mem.vhd