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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Rev 98

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Rev	Log message	Author	Age	Path
93	Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface.	JonasDC	3996d 21h	/mod_sim_exp/tags/Release_1.4/bench/vhdl/mod_sim_exp_core_tb.vhd
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4071d 23h	/mod_sim_exp/tags/Release_1.4/bench/vhdl/mod_sim_exp_core_tb.vhd
76	testbench update	JonasDC	4108d 22h	/mod_sim_exp/tags/Release_1.4/bench/vhdl/mod_sim_exp_core_tb.vhd
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4113d 17h	/mod_sim_exp/tags/Release_1.4/bench/vhdl/mod_sim_exp_core_tb.vhd
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4208d 19h	/mod_sim_exp/tags/Release_1.4/bench/vhdl/mod_sim_exp_core_tb.vhd
43	made the core parameters generics	JonasDC	4212d 12h	/mod_sim_exp/tags/Release_1.4/bench/vhdl/mod_sim_exp_core_tb.vhd
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4231d 14h	/mod_sim_exp/tags/Release_1.4/bench/vhdl/mod_sim_exp_core_tb.vhd
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4236d 22h	/mod_sim_exp/tags/Release_1.4/bench/vhdl/mod_sim_exp_core_tb.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4248d 14h	/mod_sim_exp/tags/Release_1.4/bench/vhdl/mod_sim_exp_core_tb.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4252d 20h	/mod_sim_exp/tags/Release_1.4/bench/vhdl/mod_sim_exp_core_tb.vhd

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