URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] [vhdl/] [core/] [fifo_generic.vhd] - Rev 93

Rev	Log message	Author	Age	Path
93	Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface.	JonasDC	4039d 19h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/fifo_generic.vhd
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	4043d 12h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/fifo_generic.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4107d 11h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/fifo_generic.vhd
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4156d 16h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/fifo_generic.vhd
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4167d 09h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/fifo_generic.vhd
55	updated resource usage in comments	JonasDC	4171d 09h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/fifo_generic.vhd
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4171d 09h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/fifo_generic.vhd