Rev |
Log message |
Author |
Age |
Path |
93 |
Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface. |
JonasDC |
4073d 08h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
90 |
reverted changes from previous revision, updated AXI version with testbench |
JonasDC |
4077d 02h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
89 |
updated vhdl files so now different clock frequencies are posible for the core and bus interface. |
JonasDC |
4141d 00h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4148d 10h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
75 |
made rw_address a vector of a fixed width |
JonasDC |
4185d 10h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4190d 05h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4198d 00h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4198d 06h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4285d 06h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
43 |
made the core parameters generics |
JonasDC |
4289d 00h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
41 |
removed deprecated files from version control |
JonasDC |
4295d 08h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4303d 23h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4308d 02h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4309d 01h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4309d 10h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4309d 11h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4310d 01h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4313d 10h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
23 |
added descriptive comments |
JonasDC |
4313d 11h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4316d 04h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/mod_sim_exp_pkg.vhd |