URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] [vhdl/] [core/] [modulus_ram_gen.vhd] - Rev 93

Rev	Log message	Author	Age	Path
93	Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface.	JonasDC	4039d 19h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/modulus_ram_gen.vhd
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	4043d 13h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/modulus_ram_gen.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4107d 11h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/modulus_ram_gen.vhd
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4164d 16h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/modulus_ram_gen.vhd