URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] [vhdl/] [core/] [operand_ram_asym.vhd] - Rev 93

Rev	Log message	Author	Age	Path
93	Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface.	JonasDC	4039d 19h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/operand_ram_asym.vhd
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	4043d 13h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/operand_ram_asym.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4107d 11h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/operand_ram_asym.vhd
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4133d 18h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/operand_ram_asym.vhd
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4156d 16h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/operand_ram_asym.vhd
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4156d 19h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/operand_ram_asym.vhd