URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] [vhdl/] [core/] [register_n.vhd] - Rev 101

Rev	Log message	Author	Age	Path
93	Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface.	JonasDC	4039d 17h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/register_n.vhd
15	changed generic for register width from n to width for consistency	JonasDC	4290d 10h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/register_n.vhd
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4290d 18h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/register_n.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4291d 10h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/register_n.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4295d 16h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/register_n.vhd