URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] [vhdl/] [core/] [sys_first_cell_logic.vhd] - Rev 101

Rev	Log message	Author	Age	Path
93	Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface.	JonasDC	4073d 08h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/sys_first_cell_logic.vhd
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4309d 10h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/core/sys_first_cell_logic.vhd