URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] [vhdl/] [ram/] [tdpram_asym.vhd] - Rev 99

Rev	Log message	Author	Age	Path
93	Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface.	JonasDC	4044d 08h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ram/tdpram_asym.vhd
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	4048d 01h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ram/tdpram_asym.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4112d 00h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ram/tdpram_asym.vhd
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4161d 08h	/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ram/tdpram_asym.vhd