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[/] [mod_sim_exp/] [tags/] [Release_1.4/] [sim/] [Makefile] - Rev 96

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93 Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface. JonasDC 3989d 20h /mod_sim_exp/tags/Release_1.4/sim/Makefile
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3993d 14h /mod_sim_exp/tags/Release_1.4/sim/Makefile
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS		 JonasDC 4064d 22h /mod_sim_exp/tags/Release_1.4/sim/Makefile
70 updated testbench for use with new core parameters
updated makefile, added new sources		 JonasDC 4106d 17h /mod_sim_exp/tags/Release_1.4/sim/Makefile
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package		 JonasDC 4114d 12h /mod_sim_exp/tags/Release_1.4/sim/Makefile
41 removed deprecated files from version control JonasDC 4211d 20h /mod_sim_exp/tags/Release_1.4/sim/Makefile
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4225d 22h /mod_sim_exp/tags/Release_1.4/sim/Makefile
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4225d 22h /mod_sim_exp/tags/Release_1.4/sim/Makefile
28 updated makefile for new pipeline sources JonasDC 4226d 12h /mod_sim_exp/tags/Release_1.4/sim/Makefile
24 changed names of top-level module to mod_sim_exp_core JonasDC 4229d 21h /mod_sim_exp/tags/Release_1.4/sim/Makefile
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 4241d 13h /mod_sim_exp/tags/Release_1.4/sim/Makefile

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