URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [syn/] [altera/] [log/] [operand_mem/] [asym_mes.htm] - Rev 101

Rev	Log message	Author	Age	Path
93	Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface.	JonasDC	4039d 19h	/mod_sim_exp/tags/Release_1.4/syn/altera/log/operand_mem/asym_mes.htm
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4156d 15h	/mod_sim_exp/tags/Release_1.4/syn/altera/log/operand_mem/asym_mes.htm