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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [verilog/] [generic_fifo_dc.v] - Rev 94

Rev	Log message	Author	Age	Path
94	BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include: - changed RAM and memory to support different clocks - new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org) - parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers) - added logic for control signals to cross from one clock domain to another - updated testbenches and interfaces accordingly - added log of synthesis of the 2 new fifo's for Xilinx	JonasDC	4146d 04h	/mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v