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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 102

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Rev	Log message	Author	Age	Path
94	BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include: - changed RAM and memory to support different clocks - new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org) - parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers) - added logic for control signals to cross from one clock domain to another - updated testbenches and interfaces accordingly - added log of synthesis of the 2 new fifo's for Xilinx	JonasDC	4190d 12h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4267d 19h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
77	found fault in code, now synthesizes normally	JonasDC	4302d 08h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4307d 15h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
73	updated plb interface, mem_style and device generics added	JonasDC	4308d 14h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4317d 09h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4404d 16h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
43	made the core parameters generics	JonasDC	4408d 09h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4414d 17h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
40	adjusted core instantiation to new core module name	JonasDC	4422d 21h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4448d 16h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd

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