URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 55

Rev	Log message	Author	Age	Path
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4404d 08h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
43	made the core parameters generics	JonasDC	4408d 02h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4414d 10h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
40	adjusted core instantiation to new core module name	JonasDC	4422d 14h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4448d 09h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd