URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 65

Rev	Log message	Author	Age	Path
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4697d 17h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4784d 23h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
43	made the core parameters generics	JonasDC	4788d 17h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4795d 00h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
40	adjusted core instantiation to new core module name	JonasDC	4803d 05h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4829d 00h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd