URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 76

Rev	Log message	Author	Age	Path
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4306d 23h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
73	updated plb interface, mem_style and device generics added	JonasDC	4307d 22h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4316d 17h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4404d 00h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
43	made the core parameters generics	JonasDC	4407d 17h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4414d 01h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
40	adjusted core instantiation to new core module name	JonasDC	4422d 05h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4448d 00h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd