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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 89

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Rev Log message Author Age Path
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS		 JonasDC 4266d 22h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
77 found fault in code, now synthesizes normally JonasDC 4301d 11h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4306d 18h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
73 updated plb interface, mem_style and device generics added JonasDC 4307d 17h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package		 JonasDC 4316d 12h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4403d 19h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
43 made the core parameters generics JonasDC 4407d 12h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4413d 20h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
40 adjusted core instantiation to new core module name JonasDC 4422d 00h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4447d 19h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd

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