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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [dpram_generic.vhd] - Rev 97

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Rev	Log message	Author	Age	Path
94	BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include: - changed RAM and memory to support different clocks - new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org) - parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers) - added logic for control signals to cross from one clock domain to another - updated testbenches and interfaces accordingly - added log of synthesis of the 2 new fifo's for Xilinx	JonasDC	4146d 10h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	4152d 08h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4216d 07h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd
61	updated comments, added optional altera constraint	JonasDC	4273d 15h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4276d 05h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4276d 06h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd

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