URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [dpramblock_asym.vhd] - Rev 90

Rev	Log message	Author	Age	Path
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	4194d 21h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4258d 19h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4268d 06h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4308d 04h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd