URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [tdpram_asym.vhd] - Rev 91

Rev	Log message	Author	Age	Path
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	4152d 08h	/mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4216d 07h	/mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4265d 15h	/mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd