URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [tdpramblock_asym.vhd] - Rev 102

Rev	Log message	Author	Age	Path
94	BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include: - changed RAM and memory to support different clocks - new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org) - parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers) - added logic for control signals to cross from one clock domain to another - updated testbenches and interfaces accordingly - added log of synthesis of the 2 new fifo's for Xilinx	JonasDC	4156d 13h	/mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	4162d 12h	/mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4226d 10h	/mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4235d 21h	/mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4275d 19h	/mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd