URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Rev 67

Rev	Log message	Author	Age	Path
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4127d 18h	/mod_sim_exp/trunk/sim/Makefile
41	removed deprecated files from version control	JonasDC	4225d 01h	/mod_sim_exp/trunk/sim/Makefile
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4239d 04h	/mod_sim_exp/trunk/sim/Makefile
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4239d 04h	/mod_sim_exp/trunk/sim/Makefile
28	updated makefile for new pipeline sources	JonasDC	4239d 18h	/mod_sim_exp/trunk/sim/Makefile
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4243d 03h	/mod_sim_exp/trunk/sim/Makefile
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4254d 19h	/mod_sim_exp/trunk/sim/Makefile