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[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Rev 97

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97 changes in makefile, and fifo's are now also in mod_sim_exp library JonasDC 4184d 04h /mod_sim_exp/trunk/sim/Makefile
96 minor makefile update JonasDC 4185d 04h /mod_sim_exp/trunk/sim/Makefile
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx		 JonasDC 4198d 01h /mod_sim_exp/trunk/sim/Makefile
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4203d 23h /mod_sim_exp/trunk/sim/Makefile
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS		 JonasDC 4275d 08h /mod_sim_exp/trunk/sim/Makefile
70 updated testbench for use with new core parameters
updated makefile, added new sources		 JonasDC 4317d 03h /mod_sim_exp/trunk/sim/Makefile
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package		 JonasDC 4324d 22h /mod_sim_exp/trunk/sim/Makefile
41 removed deprecated files from version control JonasDC 4422d 05h /mod_sim_exp/trunk/sim/Makefile
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4436d 08h /mod_sim_exp/trunk/sim/Makefile
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4436d 08h /mod_sim_exp/trunk/sim/Makefile
28 updated makefile for new pipeline sources JonasDC 4436d 22h /mod_sim_exp/trunk/sim/Makefile
24 changed names of top-level module to mod_sim_exp_core JonasDC 4440d 07h /mod_sim_exp/trunk/sim/Makefile
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 4451d 23h /mod_sim_exp/trunk/sim/Makefile

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