OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [README.md] - Rev 8

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
8 added missing FENCE instruction; added optional Zifencei CPU extension zero_gravity 1605d 18h /neorv32/trunk/README.md
7 removed "mtinst" CSR since it is not ratified yet by the RISC-V specs zero_gravity 1605d 21h /neorv32/trunk/README.md
6 new processor version: 1.0.0.0 -> increased performance; debugged errors; processor now passes risc-v compliance tests; see changelog for more information zero_gravity 1606d 17h /neorv32/trunk/README.md
4 see NEORV32.pdf for changelog zero_gravity 1615d 02h /neorv32/trunk/README.md
3 general updates, see changelog in NEORV32.pdf for more information zero_gravity 1616d 20h /neorv32/trunk/README.md
2 - initial commit zero_gravity 1617d 21h /neorv32/trunk/README.md

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.