URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [lib/] [include/] [neorv32.h] - Rev 8

Rev	Log message	Author	Age	Path
8	added missing FENCE instruction; added optional Zifencei CPU extension	zero_gravity	1602d 06h	/neorv32/trunk/sw/lib/include/neorv32.h
7	removed "mtinst" CSR since it is not ratified yet by the RISC-V specs	zero_gravity	1602d 08h	/neorv32/trunk/sw/lib/include/neorv32.h
6	new processor version: 1.0.0.0 -> increased performance; debugged errors; processor now passes risc-v compliance tests; see changelog for more information	zero_gravity	1603d 04h	/neorv32/trunk/sw/lib/include/neorv32.h
4	see NEORV32.pdf for changelog	zero_gravity	1611d 14h	/neorv32/trunk/sw/lib/include/neorv32.h
3	general updates, see changelog in NEORV32.pdf for more information	zero_gravity	1613d 07h	/neorv32/trunk/sw/lib/include/neorv32.h
2	- initial commit	zero_gravity	1614d 08h	/neorv32/trunk/sw/lib/include/neorv32.h