URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [Documents/] [CPU Instruction Set_files/] [sheet001.htm] - Rev 332

Rev	Log message	Author	Age	Path
328	Documentation cleanup. Also added operand definitions.	jshamlet	451d 16h	/open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet001.htm
312	Added o8_timer24.vhd as a more flexible alternative to o8_sys_timer_ii.vhd. Also cleaned up some comments in the HTML documentation	jshamlet	583d 19h	/open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet001.htm
311	Updated documentation to reflect generic switch controlling ROR/ROL behavior and the carry bit	jshamlet	627d 15h	/open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet001.htm
277	Fixed documentation errors related to flags. The UPP ALU instruction only alters the C flag, not the Z or N flags. This implies that using indexed loads or stores with auto post-increment will potentially alter the C flag.	jshamlet	1473d 17h	/open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet001.htm
272	Updated the HTML documentation to reflect the removed generic.	jshamlet	1520d 16h	/open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet001.htm
241	Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation.	jshamlet	1688d 12h	/open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet001.htm