OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [Open8_pkg.vhd] - Rev 202

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1715d 16h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
189 Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals.		 jshamlet 1728d 14h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
188 Added a generic to alter the behavior of RTI so that it can optionally skip restoring the general purpose flags GP4 to GP7, allowing ISR's to make persistent changes to them. Also exported these flags to the top level for use outside the CPU. jshamlet 1728d 16h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
187 Added the CPU_Halt input, only now as an input to the instruction decoder. The CPU_Halt line will assert the registered CPU_Halt_Req, which will cause the instruction decoder to abort the current instruction, reset the PC, then enter a hold state until the line is deasserted. Additionally, a very minor bug that could cause the SMSK instruction to effectively execute twice if interrupted was fixed. Lastly, cleaned up the comments even more. jshamlet 1730d 13h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
186 Merged the interrupt override logic into the case structure, simplifying how interrupts are processed. jshamlet 1733d 12h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
185 1) Fixed an apparently long-standing bug where the interrupt bit wasn't being cleared after an RTI
2) Modified the program counter logic to be simpler. It now always increments, and states control the increment using the offset field. A new set of constants was added to replace the old states.
3) Modified the ALU to always use Operand1 instead of ALU_Ctrl.Data (and removed the field in the record). A new ALU command, ALU_GMSK, was added, as it was the only instruction to set the .Data field to something other than Operand1 (Int_Mask)
4) Modified the package file so that flag names match what the assembler calls them. FL_Z is now PSR_Z, FL_GP1 is now PSR_GP4, etc.
5) Cleaned up the comments and code formatting		 jshamlet 1733d 15h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
183 Renamed core to o8_cpu to match new naming scheme jshamlet 1735d 15h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
182 Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. jshamlet 1735d 15h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
181 Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. jshamlet 1736d 12h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
172 General code cleanup jshamlet 3260d 13h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3315d 14h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
153 Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded,
Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.		 jshamlet 4918d 05h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
151 Fixed STO instruction and interrupt logic to avoid address bus corruption issues. jshamlet 4928d 08h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
10 corrected implementation for BTT to match V8/ARClite definition, changed sense of reset, corrected comments to match source values khays 5069d 17h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
8 Need to learn SVN... jshamlet 5398d 04h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
7 Initial Upload jshamlet 5398d 04h /open8_urisc/trunk/open8_urisc/VHDL/Open8_pkg.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.