URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [async_ser_tx.vhd] - Rev 317

Rev	Log message	Author	Age	Path
295	Undoing previous revision. UART was fine, bug reporter was not.	jshamlet	1177d 08h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd
294	Fixed an ancient bug in the parity logic that had the parity inverted.	jshamlet	1177d 13h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd
220	More revision sections added	jshamlet	1694d 08h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd
218	Revision sections added, vdsm8.vhd added.	jshamlet	1694d 08h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd
216	Fixed missing parenthesis	jshamlet	1694d 10h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd
215	More code cleanup	jshamlet	1694d 11h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd
209	Fixed an issue in the PIT timer that caused an immediate interrupt on interval write, Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register, While cleaning elsewhere, founding a spacing issue in the CPU HDL, Added a 4k ROM and MW core.	jshamlet	1700d 04h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd
208	Removed unnecessary package references	jshamlet	1700d 13h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd
207	Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics.	jshamlet	1701d 06h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd